1. Technical Field
The present invention relates to resistance semiconductor memory devices. More particularly, the present invention relates to a resistance semiconductor memory device having a three-dimensional stack structure and a word line decoding method thereof, which is capable of obtaining an efficient word line decoding.
2. Discussion of Related Art
Nonvolatile memory device typically exhibit high capacity and low power consumption. Exemplary memory devices in this regard include, PRAM (Phase-change Random Access Memory), RRAM (Resistance random access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferro-electric Random Access Memory), etc.
MRAM uses a scheme of storing data by using a change of magnetization direction in a tunnel junction. FRAM uses a scheme of storing data by using a ferroelectric polarization characteristic. These memories typically have a high degree of integration, high speed operation, drive with low power, good retention of data, etc.
PRAM uses a scheme of storing data by using a change of resistance value based on a phase change of phase-change material. The phase change material may be chalcogenide, in which a phase is changed according to a temperature change, wherein the phase change affects a change in resistance thereof. The phase change material may be GexSbyTez (hereinafter, referred to as ‘GST’) as the alloy of Ge (germanium), Sb (antimony) and Te (tellurium).
A phase of the phase change material is fast changeable between an amorphous state and a crystalline state according to temperature.
An RRAM (resistance random access memory) typically uses a characteristic such as a resistance change where a resistance value based on a voltage of complex metal oxides is changed.
A memory cell structure of a resistance semiconductor memory device using a resistance change material may be classified as one of a transistor structure and a diode structure. In the transistor structure, transistors are employed as switching devices. In the diode structure, diode is employed as switching device.
As compared with semiconductor memory devices employing the transistor structure, semiconductor memory devices employing the diode structure can allow, a write current, a greater current which increases exponentially. For this reason, it is possible to manufacture semiconductor memory devices employing the diode structure smaller than semiconductor memory devices employing the transistor structure.
FIG. 1 illustrates a memory cell structure of a resistance semiconductor memory device.
Referring to FIG. 1, a memory cell M of the resistance semiconductor memory device includes one diode D and one variable resistance device R. The variable resistance device is formed of complex metal oxides as described above.
The diode D of the memory cell M is coupled between a word line WL and the variable resistance device R. For example, a cathode terminal may be coupled to the word line WL and an anode terminal may be coupled to one end of the variable resistance device R. The variable resistance device R is coupled between the diode D and a bit line BL.
In the resistance semiconductor memory device employing a memory cell of the diode structure described above, a write operation is performed by using a reversible characteristic of the variable resistance device R based on a magnitude of current or a voltage applied to a memory cell through the bit line BL, and by using the variable resistance device R as a data storage element. In the write operation to memory cell M, when current or voltage is supplied through the bit line BL and the word line WL transitions to a low level or ground level, a forward bias is applied to the diode D, thus forming a current path in a direction of from the bit line BL to the word line WL.
A logic state of data written thereto is decided according to a level of voltage applied to the bit line BL. For example, when a write voltage of a level corresponding to data ‘0’ is applied, the data ‘0’ is written, and when a write voltage of a level corresponding to data ‘1’ is applied, the data ‘1’ is written.
In a read operation, data is decided with an amount of current flowing through memory cell according to a state of the memory cell. That is, a read voltage of a given level is applied to memory cell M, and a change in current flowing from the bit line BL to the word line WL is measured, whereby a logic state of data can be decided.
As semiconductor memory devices become increasingly high-integrated, a resistance semiconductor memory device having a memory cell of the diode structure described above will be increasing implemented. In such high integration applications, particularly in two dimensional structures, are approaching a limit. Thus, there have been endeavors to realize semiconductor memory devices having a three-dimensional structure to overcome the limit of the two dimensional structure. In realizing the semiconductor memory device of three-dimensional structure, a layout structure including word lines and an efficient method of decoding the word lines are needed.